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NAU8224 datasheet rev 1.0 page 1 of 27 aug, 2012 NAU8224 3.1w stereo filter-free class-d audio amplifier with 2 wire interface gain control 1 description the NAU8224 is a stereo high efficiency filter-free class-d audio amplifier, which is capable of drivi ng a 4 load with up to 3.1w output power. this device provides chip enable pin with extremely low standby current and f ast start-up time of 3.4ms. the NAU8224 features a highly flexible 2 wire interface with many useful gain settings. the gain can be selected from 24db to -62db (plus mute) by using 2 wire interface and gs pin. the NAU8224 is ideal for the portable applications of battery drive, as it has advanced features like 87db psrr, 91% efficiency, ultra low quiescent current (i.e. 2.1ma at 3.7v for 2 channels) and superior emi performan ce. it has the ability to configure the inputs in either single-en ded or differential mode. NAU8224 is available in miniature qfn-20 package. key features low quiescent current: ? 2.1ma at 3.7v for 2 channels ? 3.2ma at 5v for 2 channels gain setting with 2 wire interface and gs pin ? 24db to -62db (plus mute) powerful stereo class-d amplifier: ? 2ch x 3.1w (4 @ 5v, 10% thd+n) ? 2ch x 1.26w (4 @ 3.7v, 1% thd+n) ? 2ch x 1.76w (8 @ 5v, 10% thd+n) ? 2ch x 0.76w (8 @ 3.7v, 1% thd+n) low output noise: 20 v rms @0db gain 87db psrr @217hz low current shutdown mode click-and pop suppression applications notebooks / tablet pcs personal media players / portable tvs mp3 players portable game players digital camcorders figure 1: NAU8224block diagram
NAU8224datasheet rev 1.0 page 2 of 27 aug, 2012 2 pinout- qfn 20 (top view) part number dimension package package material NAU8224yg 4mm x 4mm qfn-20 pb-free
NAU8224datasheet rev 1.0 page 3 of 27 aug, 2012 3 pin descriptions qfn name type functionality 1 outrp analog output right channel positive btl ou tput 2 vdd supply power supply 3 nc nc no connect 4 en digital input chip enable (high = enable; low = pd) 5 inr analog input right channel negative input 6 ipr analog input right channel positive input 7 gs analog input 5 selectable gain setting (0db / 6db / 12db / 18db / 24db) 8 vdd supply power supply 9 vss supply ground 10 ipl analog input left channel positive input 11 inl analog input left channel negative input 12 sclk digital input i2c serial clock 13 sdio digital i/o i2c serial data input & output 14 vdd supply power supply 15 outlp analog output left channel positive btl ou tput 16 vss supply ground 17 outln analog output left channel negative btl ou tput 18 vdd supply power supply 19 outrn analog output right channel negative btl o utput 20 vss supply ground 21 ex-pad analog input thermal tab (must be connect ed to vss, qfn-20 package, only) notes 1. pins designated as nc (not internally connected) sh ould be left as no-connection table 1: NAU8224 pin description
NAU8224datasheet rev 1.0 page 4 of 27 aug, 2012 4 electrical characteristics conditions: en = vdd = 5v, vss = 0v, av = 12db z l = , bandwidth = 20hz to 22khz, t a = 25 c parameter symbol comments/conditions min typ max units power delivered output power (per channel) p out z l = 4 + 33h thd + n = 10% vdd = 5.0v 3.1 w vdd = 3.7v 1.57 z l = 4 + 33h thd + n = 1% vdd = 5.0v 2.46 vdd = 3.7v 1.26 z l = 8 + 68h thd + n = 10% vdd = 5.0v 1.76 vdd = 3.7v 0.95 z l = 8 + 68h thd + n = 1% vdd = 5.0v 1.41 vdd = 3.7v 0.76 parameter symbol comments/conditions min typ max units chip enable (en) voltage enable high v en_h vdd = 2.5v to 5.5v 1.4 v voltage enable low v en_l vdd = 2.5v to 5.5v 0.4 v input leakage current -1 +1 a thermal and current protection thermal shutdown temperature 130 c thermal shutdown hysteresis 15 c short circuit threshold i limit 2.1 a gain setting voltage gain a v tie gs to vss 24 db gs connect vss through 100k 5% 18 tie gs pin to vdd 12 gs connect vdd through 100k 5% 6 floating node 0 differential input resistance r in a v = 24db 35 k a v = 18db 70 a v = 12db 140 a v = 6db 280 a v = 0db 558
NAU8224datasheet rev 1.0 page 5 of 27 aug, 2012 electrical characteristics (continued) conditions: en = vdd = 5v, vss = 0v, av = 12db, z l = , bandwidth = 20hz to 22khz, t a = 25 c parameter symbol comments/conditions min typ max units normal operation quiescent current consumption i qui vdd = 3.7v 2.1 ma vdd = 5v 3.17 ma shut down current i off en = 0 0.1 a oscillator frequency f osc 300 khz efficiency 91 % start up time t start 3.4 msec output offset voltage v os 1 4 mv common mode rejection ratio cmrr f in = 1khz 80 db click-and-pop suppression into shutdown (z l =8 ) a weighted -72 dbv power supply rejection ratio dc psrr vdd = 2.5v to 5.5v 98 db ac psrr* v ripple = 0.2vpp@217hz** v ripple = 0.2vpp@1khz v ripple = 0.2vpp@10khz 87 74 54 db channel crosstalk f in = 1khz, z l = 8 + 68h -101 db * measured with 0.1uf capacitor on v dd and battery supply ** meas ured with 2.2uf input capacitor. parameter symbol comments/conditions min typ max units noise performance av = 0db (a-weighted) 20 v rms av = 6db (a-weighted) 21 av = 12db (a-weighted) 27 av = 18db (a-weighted) 36 av = 24db (a-weighted) 52 the following setup is used to measure the above pa rameters
NAU8224datasheet rev 1.0 page 6 of 27 aug, 2012 digital serial interface timing two wire control mode timing symbol description min typ max unit t stah sdio falling edge to sclk falling edge hold timing in start / repeat start condition 600 - - ns t stas sclk rising edge to sdio falling edge setup timing in repeat start condition 600 - - ns t stos sclk rising edge to sdio rising edge setup timing in stop condition 600 - - ns t sckh sclk high pulse width 600 - - ns t sckl sclk low pulse width 1,300 - - ns t rise rise time for all 2-wire mode signals - - 300 ns t fall fall time for all 2-wire mode signals - - 300 ns t sdios sdio to sclk rising edge data setup time 100 - - n s t sdioh sclk falling edge to sdio data hold time 0 - 600 n s
NAU8224datasheet rev 1.0 page 7 of 27 aug, 2012 digital serial interface electrical characteristics condition min typ. max. unit test conditions input leakage current sclk, sdio -1 - +1 a vdd = 5.5v input high voltage vih 0.7 vdd 5.5 v input low voltage vil vss 0.3 vdd v voh (sclk, sdio) 0.9 vdd v vol (sclk, sdio) 0.2 vdd v iol = 1 ma sdio, sclk; pull up resistor value 50k ohm absolute maximum ratings condition min max units analog supply -0.50 +5.50 v industrial operating temperature -40 +85 c storage temperature range -65 +150 c caution: do not operate at or near the maximum rati ngs listed for extended periods of time. exposure to such conditions may adversely influence product reliability and result in failures not covered by warranty. operating conditions condition symbol min typical max units analog supply range vdd 2.50 3.7 5.50 v ground vss 0 v
NAU8224datasheet rev 1.0 page 8 of 27 aug, 2012 6 special feature description the NAU8224 offers excellent quantity performance a s high efficiency, high output power and low quiesc ent current. it also provides the following special features. 6.1 gain setting with 2 wire interface control the NAU8224 has a gs pin, which can control five se lectable gain settings (i.e. 0db / 6db / 12db / 18d b / 24db). gs pin configuration internal gain (db) gs tie to vss 24 gs connect to vss through 100k 5% resistor 18 gs tie to vdd 12 gs connect to vdd through 100k 5% resistor 6 floating (open node) 0 the NAU8224 provides 2 wire register programmable v olume control in addition to the gs pin selectable gain selection. the possible gain values by using these two control s are listed in the table below:
NAU8224datasheet rev 1.0 page 9 of 27 aug, 2012 vlcrtl[5:0] reg 0x1b gaindec[4:0]=0x01 (gs pin set to 0db position) gaindec[4:0]=0x02 (gs pin set to 6db position) gaindec[4:0]=0x04 (gs pin set to 12db position) gaindec[4:0]=0x08 (gs pin set to 18db position) gaindec[4:0]=0x10 (gs pin set to 24db position) 0x0 0 db 6 db 12 db 18 db 24 db 0x1 -2 db 4.1 db 10.4 db 17 db not used 0x2 -4 db 2.2db 8.8 db 16 db not used 0x3 -6 db 0.4 db 7.1db 15 db not used 0x4 -8 db -1.6 db 5.4 db 13.7 db not used 0x5 -10 db -3.5 db 3.6 db 12.4 db not used 0x6 -12 db -5.6 db 1.7 db 10.9 db not used 0x7 -14 db -7.5 db -0.2 db 9.4 db not used 0x8 -16 db -9.5 db -2 db 7.9 db not used 0x9 -18db -11.4 db -3.9 db 6.2 db not used 0xa -20db -13.4 db -5.8 db 4.5 db not used 0xb -22db -15.4 db -7.8 db 2.7 db not used 0xc -24db -17.3 db -9.7 db 0.9 db not used 0xd -26 db -19.3 db -11.7 db -0.9 db not used 0xe -28 db -21.3 db -13.6 db -2.8 db not used 0xf -30 db -23.3 db -15.6 db -4.7 db not used 0x10 -32 db -25.3 db -17.6 db -6.6 db not used 0x11 -34 db -27.3 db -19.3 db -7.3 db not used 0x12 -36 db -29.1 db -20.4 db -7.3 db not used 0x13 -38 db -30.7 db -20.5 db -7.2 db not used 0x14 -40 db -32.2 db -20.2 db -7.1 db not used 0x15 -42 db -33.7 db -20 db -7.1 db not used 0x16 -44 db -35.1 db -19.8 db -7.1 db not used 0x17 -46 db -36.6 db -19.7 db -7.1 db not used 0x18 -48 db -36 db -19.6 db -7.0 db not used 0x19 -50 db -35.2 db -19.5 db -7.0 db not used 0x1a -52 db -34.6 db -19.5 db -7.0 db not used 0x1b -54 db -34.2 db -19.4 db -7.0 db not used 0x1c -56 db -33.9 db -19.4 db -7.0 db not used 0x1d -58 db -33.7 db -19.4 db -7.0 db not used 0x1e -60db -33.5 db -19.4 db -7.0 db not used 0x1f -62 db -33.4 db -19.3 db -7.0 db not used 0x3f mute mute mute mute mute
NAU8224datasheet rev 1.0 page 10 of 27 aug, 2012 6.1.1 2-wire-serial control and data bus (i 2 c style interface) the serial interface provides a 2-wire bidirectiona l read/write data interface similar to and typicall y compatible with standard i2c protocol. this protocol defines any d evice that sends clk onto the bus as a master, and the receiving device as slave. the NAU8224 can function only as a slave device. an external clock drives the device, and in accorda nce with the protocol, data is sent to or from the device accordingly. all functions are controlled by means of a register control interface in the device. 6.1.2 2-wire protocol convention all 2-wire interface operations must begin with a s tart condition, which is a high-to-low transition o f sdio while sclk is high. all 2-wire interface operations are terminated by a stop condition, which is a low to h igh transition of sdio while sclk is high. a stop cond ition at the end of a read or write operation place s the serial interface in standby mode. an acknowledge (ack), is a software convention is u sed to indicate a successful data transfer. the t ransmitting device releases the sdio bus after transmitting eight bits to allow for the ack response. during the ninth c lock cycle, the receiver pulls the sdio line low to acknowledge the reception of the eight bits of data. following a start condition, the master must output a device address byte. this consists of a 7-bit d evice address, and the lsb of the device address byte is the r/w (read /write) control bit. when r/w= 1, this indicates t he master is initiating a read operation from the slave device, and when r/w=0, the master is initiating a write op eration to the slave device. if the device address matches the address of the slave device, the slave will output an ack d uring the period when the master allows for the ack signal. start and stop signals 9 8 1 2 ...7 acknowledge sclk sdio not acknowledge acknowledge and not acknowledge
NAU8224datasheet rev 1.0 page 11 of 27 aug, 2012 device address byte control address byte data byte 0 1 0 1 0 1 0 r/w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 slave address byte, control address byte, and data byte 6.1.3 2-wire write operation a write operation consists of a two-byte instructio n followed by a data byte. a write operation requi res a start condition, followed by a valid device address byte with r/w= 0, a valid control address byte, data byt e, and a stop condition. the NAU8224 is permanently programmed with ? 010 1010 ? (0x2a) as the device address. if the device addr ess matches this value, the NAU8224 will respond with t he expected ack signaling as it accepts the data be ing transmitted into it. write sequence 6.1.4 2-wire single read operation a read operation consists of a three-byte write ins truction followed by a read instruction of data by te. the bus master initiates the operation issuing the following seque nce: a start condition, device address byte with t he r/w bit set to ?0?, and a control register address byte. this ind icates to the slave device which of its control reg isters is to be accessed. the NAU8224 is permanently programmed with ?010 101 0? (0x2a) as its device address. if the device addr ess matches this value, the NAU8224 will respond with the expec ted ack signaling as it accepts the control registe r address being transmitted into it. after this, the master transm its a second start condition, and a second instanti ation of the same device address, but now with r/w=1. after again recognizing its device address, the nau 8224 transmits an ack, followed by a one byte value containing the data from the selected control register inside the NAU8224. during this phase, the master generates th e ack signaling with byte transferred from the NAU8224.
NAU8224datasheet rev 1.0 page 12 of 27 aug, 2012 ack ack start device address[6:0] = 0101010 reg addr[7:0] write device id [6:0] read repeat start ack read data[7:0] of reg addr host should not drive ack right before host wants to issue stop. sclk sdio 1 2 .. 7 8 9 1 2 .. 8 9 1 2 .. 8 9 1 2 .. 7 8 9 stop read sequence 6.1.5 2-wire timing the NAU8224 is compatible with serial clock speeds defined as ?standard mode? with sclk 0 - 100 khz, a nd ?fast mode? with sclk 0 - 400 khz. at these speeds, the t otal bus line capacitance load is required to be 40 0 pf or less. open collector drivers are required for the serial interface. therefore, the bus line rise time is det ermined by the total serial bus capacitance and the vdd pull-up resistor s. the NAU8224 defaults to a weak pull up (typical 50 k ohm) for applications with no external pull up resistor. 6.2 register map the nau8223 contains the registers as shown in the table below. addr (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 default (hex) note 04 gaindec[4:0] 01 ro 1b volctrl[5] volctrl[4] volctrl[3] volctrl[2] volctrl [1] volctrl[0] 00 rw
NAU8224datasheet rev 1.0 page 13 of 27 aug, 2012 6.3 register map details 0x04:reggain this register is a read only register and can be u sed to check the function of the gain pin. bit default function when read ?1? gaindec[4] 0 24 db gain setting enabled gaindec[3] 0 18 db gain setting enabled gaindec[2] 0 12 db gain setting enabled gaindec[1] 0 6 db gain setting enabled gaindec[0] 0 0 db gain setting enabled 0x1b: volctrl[5:0] this register can be used to adjust the output vol ume. bit default function when set to ?1? volctrl[5] 0 adjust output volume volctrl[4] 0 adjust output volume volctrl[3] 0 adjust output volume volctrl[2] 0 adjust output volume volctrl[1] 0 adjust output volume volctrl[0] 0 adjust output volume 6.4 device protection the NAU8224 includes device protection for three op erating scenarios. they are 1. thermal overload 2. short circuit 3. supply under voltage 6.4.1 thermal overload protection when the device internal junction temperature reach es 130c, the NAU8224 will disable the output drive rs. when the device cools down and a safe operating temperature of 115c has been reached for at least about 47ms, the output drivers will be enabled again. 6.4.2 short circuit protection if a short circuit is detected on any of the pull-u p or pull-down devices on the output drivers for at least 14s, the output drivers will be disabled for 47ms. the output drive rs will then be enabled again and check for the sho rt circuit. if the
NAU8224datasheet rev 1.0 page 14 of 27 aug, 2012 short circuit is still present, the output drivers are disabled after 14s. this cycle will continue u ntil the short circuit is removed. the short circuit threshold is set at 2.1a . 6.4.3 supply under voltage protection if the supply voltage drops under 2.1v, the output drivers will be disabled while the NAU8224 control circuitry still operates. this will avoid the battery supply to dra g down too low before the host processor can safely shut down the devices on the system. if the supply drops further below 1.0v the internal power on reset activated an d puts the entire device in power down state. 6.5 power up and power down control when the supply voltage ramps up, the internal powe r on reset circuit gets triggered. at this time all internal circuits will be set to power down state. the device can be enabl ed by setting the en pin high. upon setting the en pin high, the device will go through an internal power up sequenc e in order to minimize ?pops? on the speaker output . the complete power up sequence will take about 3.4ms. the device will power down in about 30s, when the en pin is set low. it is important to keep the input signal at zero am plitude or enable the mute condition in order to mi nimize the ?pops? when the en pin is toggled. .
NAU8224datasheet rev 1.0 page 15 of 27 aug, 2012 7 typical operating characteristics conditions: en = v dd = 5v, vss = 0v, av = 12db, z l = , bandwidth = 20hz to 22khz, t a = 25c, unless otherwise noted 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficiency(%) output power(w) efficiency vs output power (v dd = 5.0v) zl=4 ?+33 uh zl=8?+68uh 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 efficiency(%) output power(w) efficiency vs output power (v dd = 3.7v) zl=4 ?+ 33 uh zl=8? +68uh 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 3.7v, zl= 8? + 68uh) pout 0.2w pout 0.4w 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 4.2v, zl= 8? + 68uh) pout 0.2w pout 0.6w
NAU8224datasheet rev 1.0 page 16 of 27 aug, 2012 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 5v, zl= 8? + 68uh) pout 0.2w pout 1.2w 0.001 0.01 0.1 1 10 0 0.5 1 1.5 thd+n (%) pout (w) thd+n vs pout (v dd = 3.7v, zl = 8? + 68uh) f 100hz f 1khz f 6khz 0.001 0.01 0.1 1 10 0 0.5 1 1.5 2 thd+n (%) pout (w) thd+n vs pout (v dd = 4.2v, zl= 8? + 68uh) f 100hz f 1khz f 6khz 0.001 0.01 0.1 1 10 0 1 2 3 thd+n (%) pout (w) thd+n vs pout (v dd = 5v, zl=8? + 68uh) f 100hz f 1khz f 6khz
NAU8224datasheet rev 1.0 page 17 of 27 aug, 2012 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 3.7v, zl= 4? + 33uh) pout 0.2w pout 0.8w 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 4.2v, zl= 4? + 33uh) pout 0.2w pout 1w 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency (hz) thd+n vs frequency (v dd = 5v, zl= 4? + 33uh ) pout 1.5w pout 2w 0.001 0.01 0.1 1 10 0 1 2 3 thd+n (%) pout (w) thd+n vs pout (v dd = 3.7v, zl= 4? + 33uh) f = 100hz f = 1khz f = 6khz
NAU8224datasheet rev 1.0 page 18 of 27 aug, 2012 0.001 0.01 0.1 1 10 0 1 2 3 thd+n (%) pout (w) thd+n vs pout (v dd = 4.2v, zl= 4? + 33uh) f = 100hz f = 1khz f = 6khz 0.001 0.01 0.1 1 10 0 1 2 3 4 thd+n (%) pout (w) thd+n vs pout (v dd = 5v, zl= 4? + 33uh) f = 100hz f = 1khz f = 6khz -10 -5 0 5 10 15 20 25 30 20 200 2000 20000 gain (db) frequency (hz) gain vs frequency gain 0db gain 6db gain 12db gain 18db gain 24db -120 -100 -80 -60 -40 -20 0 20 200 2000 20000 level (db) frequency (hz) crosstalk vs frequency left to right right to left
NAU8224datasheet rev 1.0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 2.5 3.5 4.5 psrr (db) supply voltage (v) ac psrr vs supply voltage psrr @gain 0db, 1khz page 19 of 27 aug, 2012 5.5 6.5 supply voltage (v) ac psrr vs supply voltage psrr @gain 0db, 1khz -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20 200 2000 psrr (db) frequency (hz) ac psrr vs frequency psrr @ gain 0db aug, 2012 20000 frequency (hz) ac psrr vs frequency psrr @ gain 0db
NAU8224datasheet rev 1.0 page 20 of 27 aug, 2012 0 0.5 1 1.5 2 2.5 3 3.5 2.5 3.5 4.5 5.5 supply current(ma) supply voltage (v) supplyvoltage vs supplycurrent
NAU8224datasheet rev 1.0 page 21 of 27 aug, 2012 8 application information 8.1 application diagram vss outlp vdd ipl vdd en vss vdd sdio gs vdd vss nc inr ipr outln sclk outrn outrp 2 3 4 5 6 7 8 1 10 15 14 13 12 11 16 9 20 19 18 17 inl NAU8224 stereo class d qfn 20-pin vdd 100k optional 100k optional 10uf 0.1uf 0.47uf 0.47uf 0.47uf 0.47uf 0.1uf 10uf 10uf 0.1uf 10uf 0.1uf vdd vdd vdd vdd shutdown control left single ended input right single ended input sclk sdio p.s. gs pin ? the 100k resistors are optional. gs can be floating for int ernal gain setting = 0db. please refer section 6.1 (gain setting) for the detailed explanation.
NAU8224datasheet rev 1.0 page 22 of 27 aug, 2012 8.2 component selection coupling capacitors an ac coupling capacitor (c in ) is used to block the dc content from the input so urce. the input resistance of the amplifier (r in ) together with the c in will act as a high pass filter. so depending on th e required cut off frequency the c in can be calculated by using the following formula
where
is the desired cut off frequency of the high pass filter. bypass capacitors bypass capacitors are required to remove the ac rip ple on the vdd pins. the value of these capacitors depends on the length of the vdd trace. in most cases, 10uf and 0. 1uf are enough to get the good performance. 8.3 layout considerations the NAU8224 qfn package uses an exposed pad on the bottom side of the package to dissipate excess powe r from the output drivers. this pad must be soldered carefully to the pcb for proper operation of the NAU8224. th is pad is internally connected to vss. a typical layout is sh own below.
NAU8224datasheet rev 1.0 page 23 of 27 aug, 2012 the pcb has to be designed in such a manner that it should have nine vias in 3x3 grid under NAU8224. t he vias should have hole size of 12mil and a spacing of 30mils. th e pad size of the vias is 24mils. the vias on the t op side of the board should be connected with a copper pour that has an area of 2mm x 2mm, centered underneath the NAU8224. the nine vias should connect to copper pour area on the bott om of the pcb. it is preferred to pour the complete bottom side of the board with vss. also good pcb layout and grounding techniques are e ssential to get the good audio performance. it is better to use low resistance traces as these devices are driving low impedance loads. the resistance of the traces has a significant effect on the output power delivered to the load. in order t o dissipate more heat, use wide traces for the powe r and ground lines. 8.4 class d without filter the NAU8224 is designed for use without any filter on the output line. that means the outputs can be d irectly connected to the speaker in the simplest configuration. this type of filter less design is suitable for portable applications where the speaker is very close to the amplifier. in other wo rds, this is preferable in applications where the l ength of the traces between the speaker and amplifier is short. the fo llowing diagram shows this simple configuration. NAU8224 outputs connected to speaker without filter circuit 8.5 class d with filter in some applications, the shorter trace lengths are not possible because of speaker size limitations a nd other layout reasons. in these applications, the long traces wil l cause emi issues. there are two types of filter c ircuits available to reduce the emi effects. these are ferrite bead and lc filters. ferrite bead filter the ferrite bead filters are used to reduce the hig h frequency emissions. the typical circuit diagram is shown in the figure. 1nf 1 nf ferrite bead ferrite bead outlp outln NAU8224 outputs connected to speaker with ferrite b ead filter
NAU8224datasheet rev 1.0 page 24 of 27 aug, 2012 the characteristic of ferrite bead is such that it offers higher impedance at high frequencies. for be tter emi performance select ferrite bead which offers highest impedance at high frequencies, so that it will attenuate the signals at higher frequencies. usually the ferrite beads have low imp edance in the audio range, so it will act as a pass through filter in the audio frequency range. lc filter the lc filter is used to suppress the low frequency emissions. the following diagram shows the NAU8224 outputs connected to the speaker with lc filter circuit. r l is the resistance of the speaker coil. outlp outln l c c r l l NAU8224 outputs connected to speaker with lc filter standard low pass lcr filter the following are the equations for the critically damped ( = 0.707) standard low pass lcr filter

is the cutoff frequency the l and c values for differential configuration c an be calculated by duplicating the single ended co nfiguration values and substituting r l = 2r.
NAU8224datasheet rev 1.0 page 25 of 27 aug, 2012 8.6 NAU8224 emi performance the NAU8224 includes a spread spectrum oscillator f or reduced emi. the pwm oscillator frequency typica lly sweeps in a range of 300 khz +/- 15 khz in order to spread the energy of the pwm pulses over a larger frequen cy band. in addition, slew rate control on the output drivers a llows the application of ?filter less? loads, while suppressing emi at high frequencies. the below graph shows the emi per formance of NAU8224 with ferrite beads and speaker cable length of 30cm.
NAU8224datasheet rev 1.0 page 26 of 27 aug, 2012 9 package dimensions 9.1 qfn20l 4x4 mm^2, pitch:0.50 mm top vi ew bottom vi ew 11 6 20 1 5 10 15 16 16 15 11 10 6 5 1 20
NAU8224datasheet rev 1.0 page 27 of 27 aug, 2012 10 ordering information nuvoton part number description version history version date page description rev1.0 aug, 2012 n/a preliminary revision table 1: version history important notice nuvoton products are not designed, intended, author ized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy c ontrol instruments, airplane or spaceship instrumen ts, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications int ended to support or sustain life. furthermore, nuvoton products are no t intended for applications wherein failure of nuvo ton products could result or lead to a situation wherein personal inju ry, death or severe property or environmental damag e could occur. nuvoton customers using or selling these products f or use in such applications do so at their own risk and agree to fully indemnify nuvoton for any damages resulting from su ch improper use or sales. package type: y = 20-pin qfn package NAU8224 y g package material: g = pb-free package

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